Silicon design, IP, and verification tools for chip manufacturers and systems companies
Synopsys operates a massive engineering-first org (626 of 787 active roles in engineering) shipping EDA, silicon IP, and verification solutions across design, simulation, and physical implementation. The tech stack spans SystemVerilog, Verilog, design-automation languages (TCL, Perl), and core EDA platforms (Design Compiler, IC Compiler II, VC Formal), while actively adopting Kubernetes, PyTorch, and LLM frameworks (LangChain, LlamaIndex) — indicating a shift toward AI-assisted design flows. Projects cluster heavily on physical IP development, RTL-to-GDS automation, and verification integration at customer sites, aligned with their stated focus on accelerating time-to-market and reducing design-cycle friction.
Notable leadership hires: Methodology Automation Lead, Ethics & Compliance Director
Synopsys is a 10,000+ person public company headquartered in Sunnyvale, California, serving semiconductor design teams and systems manufacturers. The product portfolio spans silicon design tools (compiler and physical implementation platforms), reusable silicon IP (Designware cores, SerDes, memory blocks), and verification IP and simulation environments. Sales and product teams are lean (46 and 18 roles respectively), reflecting a developer-led and engineer-centric go-to-market. Hiring spans 25+ countries with concentration in traditional semiconductor hubs (United States, India, China, South Korea, Japan) and European R&D centers, signaling both global customer footprint and distributed engineering delivery.
Synopsys uses SystemVerilog, Verilog, TCL, Perl, Python, and proprietary tools (Design Compiler, IC Compiler II, VC Formal), plus ANSYS simulation. Adopting: Kubernetes, PyTorch, LangChain, LlamaIndex, RISC-V. Replacing TensorFlow and SAP S/4HANA.
Synopsys actively hires across 25 countries including United States, India, China, South Korea, Japan, Canada, Vietnam, Netherlands, United Kingdom, Ireland, and others.
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