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Encore Semi, Inc. Tech Stack

Semiconductor design and test engineering services for SoC and ASIC projects

Semiconductor Manufacturing San Diego, CA 51–200 employees Founded 2011 Privately Held

Encore Semi is a 51–200-person engineering services firm specializing in custom semiconductor design and validation work. The tech stack—Cadence Virtuoso, Synopsys, Calibre, SystemVerilog, UVM, Xcelium—reflects deep expertise in physical design, DFT, and design verification for advanced node work (FinFET). Hiring is accelerating with 42 senior and 4 lead engineers (out of 46 open roles), indicating capacity-building around active projects in RTL-to-gates flows, test automation, and UVM framework development.

Tech Stack 30 technologies

Core StackPython Linux MATLAB Siemens Tcl JTAG TCL Cadence Virtuoso Calibre FinFET SystemVerilog UVM Xcelium Synopsys Microchip Simulink Perl Verilog VHDL SERDES PCIe DDR4 FPGA DSP Cadence Spectre Verilog-AMS Cadence APD Ansys HFSS Altium

What Encore Semi, Inc. Is Building

◆Challenges

Customizing test sequences beyond default tool deliverables
Reducing eco cycles
Accelerating signoff readiness
Custom test sequence development
Post-silicon failure analysis
High-level customization of siemens tessent flows
Ensuring high test coverage
Improving synthesis flow

▲Active Projects

Tessent shell integration
Rtl-to-gates implementation for gf 22fdx
Advanced test solutions
Mmmc optimization
Custom test sequences
Dsp verification environments
Pattern engineering
Uvm framework development
Automated regression suites
Uvm framework improvement

Hiring Activity

Accelerating45 roles · 25 in 30d

Department

Engineering

45

Design

1

Seniority

Senior

42

Lead

4

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About Encore Semi, Inc.

Encore Semi provides custom engineering solutions and Centers of Expertise for semiconductor and electronics companies across North America. The company works on SoC design, embedded software, physical design, design verification, and functional safety (ISO 26262 automotive). Services span acceleration, performance optimization, and risk mitigation across the chip lifecycle—from front-end digital design through post-silicon failure analysis. The project mix (RTL implementation, advanced test sequences, DSP verification, MMMC optimization) and pain-point focus (eco cycle reduction, signoff readiness, test coverage) suggest a strong operational presence in design automation and test engineering for mid-to-advanced complexity ASICs and SoCs.

HeadquartersSan Diego, CA

Company Size51–200 employees

Founded2011

Hiring MarketsUnited States

Frequently Asked Questions

What technologies does Encore Semi use for chip design?

Cadence Virtuoso, Synopsys, Calibre, Xcelium, SystemVerilog, UVM, Verilog, VHDL, and MATLAB. Also uses Ansys HFSS for signal integrity and Altium for PCB work.

What is Encore Semi currently working on?

RTL-to-gates implementation for GlobalFoundries 22FDX, Tessent shell integration, UVM framework development, DSP verification, custom test sequence engineering, and automated regression suites for advanced test solutions.