Wi-Fi HaLow chip design for long-range, low-power IoT devices
Morse Micro designs fabless Wi-Fi HaLow semiconductors—a sub-1 GHz variant that extends range 10x beyond standard Wi-Fi while running on single-battery power for years. The stack reveals deep chip design maturity: Cadence and Synopsys EDA tools, SystemVerilog and Verilog-A for RTL, ARM Cortex and RISC-V targets. The project list (PHY development, silicon bring-up, firmware upper-layer stack) and senior-heavy hiring mix (6 of 11 active roles) signal a company in active tape-out cycles facing aggressive time-to-market and performance optimization pressure.
Morse Micro is a fabless semiconductor firm building Wi-Fi HaLow chips for IoT applications including surveillance, access control, industrial automation, and mobile devices. Founded in 2016 by Wi-Fi industry veterans including an original IEEE 802.11 inventor, the company operates with offices across Australia, China, India, and the U.S., serving a 51–200 person organization. The technical surface spans RF chip design (Cadence/Synopsys), embedded firmware (FreeRTOS, RT-Thread, ARM), and test infrastructure (Wireshark, Python automation) to bring IEEE 802.11ah silicon to market while managing power, footprint, and latency constraints.
Cadence and Synopsys dominate the stack for chip design. SystemVerilog and Verilog-A are used for RTL and analog modeling.
Yes. 10 of 11 active roles are engineering-focused, with 6 at senior level and 1 principal. Hiring occurs in Australia and Taiwan.
IEEE 802.11ah PHY development, silicon bring-up, firmware stack implementation, and embedded software architecture—all optimized for power, footprint, and performance.
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