Retym builds DSP silicon for optical networking in AI data centers—the connectivity layer between compute nodes. The stack (SystemVerilog, Verilog, Synopsys, Cadence, TSMC, SerDes, HFSS) reveals deep analog-mixed-signal and physical-design maturity; projects span ADC/DAC development, RTL-to-GDS flow ramp, and system-level test frameworks for a coherent optical transceiver. Hiring is heavily senior engineering (33 of 39 roles) across three countries, suggesting a post-Series-A product-in-flight scaling phase—pain points confirm this: timing closure, complex IP integration, distributed-team coordination, and low-power constraints are all signature stress points of first-silicon bringup.
Tech Stack 45 technologies
What Retym, Inc Is Building
◆Challenges
- Timing closure
- Scaling new engineering site
- Complex ip integration
- Building product from scratch
- Coordinating across locations
- Compliance with local labor laws
- Managing distributed team across time zones
- Debugging complex mixed-signal issues
- Developing high end adc/dac in advanced process
- Low power budget
▲Active Projects
- Adc/dac development for optical communication
- High end adc/dac in advanced process for optical communication
- Ramp-up rtl2gdsii flow
- Implement communication and project tracking tools
- Integrating austin site deliverables into global product development
- Soc dft strategy and architecture
- Test plan for special analog ips
- Test suite for sdk application flows
- System-level test framework for coherent dsp
- Next generation coherent optical transceiver development
Hiring Activity
Department
Seniority
Notable leadership hires: System Director, Marketing Director
