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Xcelerium Tech Stack
Fabless semiconductor company designing edge AI processors for wireless, radar, and computer vision
Xcelerium designs domain-specific processors for real-time AI inference at the network edge, built on RISC-V and targeting wireless, radar, and vision workloads. The tech stack—spanning RISC-V, MLIR, LLVM, TensorFlow Lite, and TinyRT—reveals a compiler-first architecture optimized for low-latency AI on constrained hardware. Active development across SOC design, physical implementation, and compiler infrastructure signals a vertically integrated hardware-software play moving from architecture definition into production tooling.
Tech Stack 34 technologies
Core StackPython TensorFlow PyTorch C++ MATLAB RISC-V Verilog SystemVerilog UVM C/C++ Assembly OpenGL Simulink GNU Radio MLIR IREE LLVM ASIC Synopsys CUDA OpenCL TensorFlow Lite TinyML Raspberry Pi BeagleBone Arduino ARM Cortex-M Assembly Language TensorRT XLA+4 more
What Xcelerium Is Building
◆Challenges
- Limitations of conventional cpu gpu fpga
- Low-latency execution for ai workloads
▲Active Projects
- Risc-v core development
- Soc design
- Physical implementation optimization
- Ai compiler stack development
- Runtime infrastructure optimization
- Next-generation compute platform
- Real-time physical ai compute platform
- X²pu architecture software foundation
- Compiler and sdk development for x²pu
- Performance-analysis tools for x²pu
Hiring Activity
5 roles · 5 in 30d
Department
Seniority
Company intelligence
