Fabless semiconductor processor design for edge AI and wireless communications
Xcelerium designs domain-specific processors for edge workloads combining wireless, radar, vision, and AI—a narrow but hardware-intensive focus reflected in their stack: Synopsys, RISC-V, CUDA, TensorFlow, and MLIR compiler work. The company is adopting MLIR, a signal they're building custom compiler infrastructure rather than relying on off-the-shelf toolchains. Early-stage hiring (6 open roles, all engineering, mostly senior) and recent focus on signoff automation and physical design suggest they're moving from architecture into production tape-out.
Xcelerium is a fabless semiconductor company founded in 2020 by veterans from Qualcomm, Broadcom, and Intel. The company develops high-performance, domain-specific processors optimized for converged edge workloads that combine wireless communications, radar, image processing, and machine learning. Rather than building general-purpose chips, they target narrow application domains where specialized hardware delivers significant performance or power advantages. The organization is US-based with engineering-focused hiring and minimal recent hiring velocity, consistent with a pre-revenue or early customer validation phase.
Xcelerium uses Synopsys for design, RISC-V and ARM instruction sets, CUDA and OpenCL for compute, TensorFlow/PyTorch/TensorRT for ML workloads, Verilog/SystemVerilog for RTL, and MLIR for compiler infrastructure. MATLAB and Simulink appear in modeling; GNU Radio and real-world platforms (Raspberry Pi, BeagleBone) in validation.
Xcelerium is headquartered in Irvine, California. The company was founded in 2020 and is privately held.
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