A
Ayar Labs Tech Stack
Optical interconnect silicon for AI infrastructure scaling
Ayar Labs builds photonic I/O chips designed to move data between AI processors faster and with less power than traditional copper interconnects. The stack—Synopsys (ICC2, Fusion Compiler), Cadence Innovus, SystemVerilog, SerDes protocols—reflects deep ASIC and silicon design work. Hiring is heavily weighted toward senior and principal engineers (40+ roles) with only 5 product positions, indicating a company still in silicon bring-up and design optimization phases, not yet in go-to-market scaling.
Tech Stack 91 technologies
Core StackPython Jira AutoCAD Cadence Innovus Synopsys ICC2 Synopsys Fusion Compiler Tcl Perl ARM STM32 CMIS SerDes BERT JTAG I2C JMP Minitab JEDEC NVIDIA AMD Intel SystemVerilog UVM RISC-V CHI LPDDR SRAM AWS X-Ray KLayout CMOS+61 more
AdoptingSerDes
What Ayar Labs Is Building
◆Challenges
- Reducing test time
- Energy consumption for ai data transfer
- Ai data bottlenecks
- Reducing dpm
- High volume manufacturing
- Removing bottlenecks limiting next-generation ai
- Transitioning products to mass production
- Scale-up and scale-out bandwidth needs
- Aggressive schedules
- I/o bandwidth bottlenecks
▲Active Projects
- Firmware for high-speed serdes chips
- Co-packaged optics solution
- Phi roadmap development
- Silicon bring-up for high-speed serdes and photonics
- Firmware for co-packaged optics
- Automated asic design flows
- High-speed interconnect optical systems
- Electrical-side modeling for silicon photonics i/o platform
- Design and integration of complex socs
- Silicon photonic chip verification
Hiring Activity
65 roles · 50 in 30d
Department
Seniority
Notable leadership hires: Engineering Director
Company intelligence
