Co-packaged optical I/O chiplets for AI scale-up interconnect
Ayar Labs builds silicon photonics chiplets that move data optically between AI processors, targeting the bandwidth and power limits of electrical interconnect. Its stack is pure chip development: SystemVerilog/UVM verification on Xcelium and Questa, Cadence Virtuoso and Spectre for analog design, plus SerDes and RISC-V. Accelerating, overwhelmingly senior-to-principal engineering hiring alongside manufacturing-ramp projects points to a shift from R&D toward mass production.
Notable leadership hires: Data Director, Head of Business Development
Ayar Labs is a privately held hardware company founded in 2015 and headquartered in San Jose, California. It develops co-packaged optics that replace electrical links with optical I/O, aimed at AI training and inference systems that need more bandwidth at lower latency and power. The company sells to builders of large-scale AI infrastructure and emphasizes compatibility with open standards. It employs 51–200 people and hires in the United States and India.
Ayar Labs relies on chip design and verification tools including Verilog, SystemVerilog, UVM, Xcelium, Questa, Cadence Virtuoso, Spectre and Design Compiler, plus C++, Python, FPGA and RISC-V.
Yes. Hiring is accelerating and is dominated by senior, staff and principal engineering roles in the United States and India, with leadership searches for a Data Director and Head of Business Development.
Current work includes SerDes IP verification, firmware for co-packaged optics products, silicon validation of optical chiplets, high-speed optical PHY development and a high-volume manufacturing ramp.
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Ayar Labs's technology stack, projects, and hiring signals are inferred from public hiring and company data — career pages, public listings, and company web presence — then clustered and de-duplicated. Figures are estimates that refresh over time. Read our full methodology →
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