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Etched designs proprietary ASICs for AI inference workloads, built on a stack spanning Cadence/Synopsys EDA tools, SystemVerilog/UVM verification, and PyTorch/JAX frameworks. The company is actively adopting PCIe 5.0/Gen 6 and NVLink while ramping mass production—a hiring mix heavily weighted toward senior hardware engineers (86 senior vs. 35 mid-level) reflects both the complexity of custom silicon and the scale-up phase they're in. Current pain points cluster around manufacturing yield, RDMA efficiency, and inference latency reduction.
Tech Stack 109 technologies
Core StackPython Go Rust C++ Linux PyTorch Cadence Allegro UVM SystemVerilog Perl TCL Cadence Synopsys I2C PCIe Etched ASICs Bash vLLM SGLang TPU JAX NVLink InfiniBand SIMD C/C++ RDMA x86 GPU Linux Kernel Tor+74 more
AdoptingPCIe 5.0 PCIe Gen 6 NVLink Redfish IPMI 800G Ethernet PCIe
What Etched Is Building
◆Challenges
- Performance bottlenecks
- Capacity constraints
- Ensuring reliability of inference servers
- Competitive talent markets
- Ensuring manufacturability at scale
- High yield and reliability issues
- Improving rdma efficiency
- Performance reliability issues
- Scaling production rapidly
- Reducing inference latency
▲Active Projects
- Mass production ramp
- Supply chain risk mitigation
- Observability stack with llm integration
- Recruiting systems improvement
- Next-generation ai accelerator design
- Custom ip verification for sohu
- Stress-testing ai subsystems
- Performance monitoring tools
- Performance modeling for sohu transformer architecture
- Performance benchmarking for transformer inference workloads
Hiring Activity
170 roles · 90 in 30d
Department
Seniority
Company intelligence
