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Syntiant Corp. Tech Stack
Edge AI chip design with deep learning optimization for always-on devices
Syntiant designs ultra-low-power neural network processors for edge AI, combining Verilog/SystemVerilog hardware design with a Python-based ML training stack (TensorFlow, PyTorch) and EDA tooling (Cadence, Synopsys, Mentor Graphics). The hiring velocity is accelerating with 13 engineering roles across senior and staff levels, and active projects span chip design (PPA tradeoff analysis, layout violation reduction) and ML model optimization (audio and vision for edge). Pain points cluster around high-volume production ramp, EDA ecosystem complexity, and next-generation ASIC performance — indicating mid-production maturity with infrastructure bottlenecks.
Tech Stack 45 technologies
Core StackPython TensorFlow PyTorch Linux Siemens AWS FastAPI MongoDB PostgreSQL GitLab CI/CD Jenkins Prometheus Grafana Kubernetes Docker Terraform Verilog SystemVerilog C/C++ Perl Windows Cadence Synopsys Mentor Graphics Ansys Keysight Git AWS EKS Ceph NFS+15 more
What Syntiant Corp. Is Building
◆Challenges
- Complex failure analysis
- Managing compute infrastructure
- High-volume production ramp-up
- Supporting eda environment
- Developing collaborative eda ecosystem
- Optimizing qualification plans
- Expanding defense market presence
- Developing deal pipeline
- Improving ppa for next generation asics
- Reducing layout violations
▲Active Projects
- New product introductions ramp
- Lead ppa tradeoff analysis to improve design
- Ndp profiling tool
- Audio and vision models for edge devices
- Core ml tools for syntiant neural decision processors
- Operational procedures improvement
- Prototype development for new ml approaches
- Development of new analytical techniques
- Collaborative eda ecosystem
- Ip repository migration
Hiring Activity
15 roles · 7 in 30d
Department
Seniority
Company intelligence
