MatX designs custom silicon optimized for large language model inference and training. The stack is deep systems work—Rust, C++, CUDA, SystemVerilog, and ASIC tools (Synopsys, Allegro)—with active firmware and kernel optimization projects. The hiring mix (15 engineers, 2 researchers, balanced mid/senior split) and pain-point focus on silicon methodology and cost efficiency suggest a team scaling from architecture through physical design tapeout, while grappling with the financial and operational overhead of semiconductor manufacturing.
Tech Stack 30 technologies
What MatX Is Building
◆Challenges
- Optimize for efficiency and cost
- Legacy infrastructure maintenance
- Lack of ops structure
- Scaling semiconductor startup financial operations
- Accurate accounting for wafer fabrication
- Financial visibility for tape-out milestones
▲Active Projects
- Subsystem silicon design deliverables
- Run quality evaluations
- Silicon architecture-to-design methodology
- Kernel optimization for specialized hardware
- Develop firmware loading flows for phy bring-up
- Train and optimize llms for hardware
- Implementing kernels for ml models such as transformers
- Micro-architecture sign-off reviews
- Physical design flow improvement
- Back-end automation and reporting
Hiring Activity
20 roles · 20 in 30d
Department
Seniority
Company intelligence
