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EXTOLL GmbH Tech Stack

SerDes and chiplet interconnect IP for next-generation SoCs

Computer Hardware Manufacturing Mannheim, Baden-Württemberg 11–50 employees Founded 2011 Privately Held

EXTOLL designs high-speed, low-power semiconductor IP for chiplet and system-on-chip architectures. The stack—Cadence, Virtuoso, Spectre, SystemVerilog, Xcelium, UVM—reflects a signals-and-power-focused hardware design practice. Active hiring is concentrated in senior and principal-level engineering roles across Germany and Austria, with 5 of 9 open positions posted in the last 30 days, suggesting pressure to scale verification and physical design capabilities as the company tackles multi-node porting and methodology improvements.

Tech Stack 13 technologies

Core StackPython Cadence Virtuoso Spectre TCL SystemVerilog Xcelium UVM PCIe Ethernet Bash Verilog Serdes

What EXTOLL GmbH Is Building

◆Challenges

Porting ip to new technology nodes
Addressing challenges in physical design verification
Improving internal methodology

▲Active Projects

Noc ip verification environment
Coverage closure and regression runs
Functional verification plan execution
Rtl2gds2 implementation flow
Physical design verification for interface ip
Uvm systemverilog verification environments for noc ip

Hiring Activity

Accelerating9 roles · 5 in 30d

Department

Engineering

9

Seniority

Senior

5

Principal

2

Staff

2

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About EXTOLL GmbH

EXTOLL develops semiconductor intellectual property (IP) for die-to-die interfaces, networks-on-chip (NoC), and chiplet connectivity, targeting ASIC and SoC manufacturers. Founded in 2011 and based in Mannheim, the company specializes in ultra-low-power, high-speed serializer-deserializer (SerDes) technology optimized for smallest footprint and best power-performance-area (PPA) metrics. Current work spans NoC IP verification environments, RTL-to-GDS implementation, and physical design validation across multiple technology nodes. The company operates as a privately held design house serving the global semiconductor supply chain.

HeadquartersMannheim, Baden-Württemberg

Company Size11–50 employees

Founded2011

Hiring MarketsAustria, Germany

Frequently Asked Questions

What semiconductor IP does EXTOLL design?

EXTOLL develops high-speed, low-power SerDes, Networks-on-Chip (NoC), and die-to-die interface IP for next-generation SoCs and chiplet architectures, optimized for minimal power and area footprint.

What EDA tools does EXTOLL use?

The company's stack includes Cadence Virtuoso, Spectre, Xcelium simulation, SystemVerilog, UVM, and TCL scripting for IP design, verification, and physical implementation workflows.

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