Eridu designs custom network switching silicon purpose-built for AI clusters. The tech stack reveals a fully integrated semiconductor workflow—SystemVerilog, Verilog, ASIC design tools (Synopsys, Innovus), and post-silicon validation frameworks—paired with SONiC and OCP SAI integration to run production workloads. Active projects span ASIC design, physical layout, chiplet platforms, and SDK development, while pain points cluster around communication bottlenecks in AI data centers and hardware verification velocity. The hiring mix is almost entirely senior/principal engineers (97% of headcount), indicating rapid execution on foundational silicon work rather than scaling operations.
Tech Stack 52 technologies
Core StackC++ Python PyTorch TensorFlow OpenShift SONiC C/C++ SystemVerilog Verilog ASIC ASICs UVM Perl Tcl OMNeT++ SerDes VXLAN TCP/IP UDP VLAN Innovus Synopsys Fusion Compiler Unix TCL BERT U-Boot UEFI Robot Framework strace Unix Shell+22 more
What Eridu Is Building
◆Challenges
- Reducing capital and power costs
- Communication bottlenecks limiting ai performance
- Communication bottlenecks in ai data centers
- Reliability issues
- Reliability improvement
- Accelerating hardware verification
- Reducing performance regressions
- Operations simplification
- Infrastructure bottlenecks
- Simplifying operations for ai deployments
▲Active Projects
- Networking asic development
- Post-silicon validation and tuning
- Ocp sai integration with sonic
- System module packaging for high-performance networking and compute platforms
- High-density substrate design
- Physical design of soc
- Advanced multi-die organic flip chip module
- Next-generation networking socs and disaggregated chiplet platforms
- Sdk development for ethernet switch silicon
- Implement and validate physical design signoff flows
Hiring Activity
35 roles · 35 in 30d
Department
Seniority
Company intelligence
