Eridu builds AI data center network switches from the silicon up, and its stack shows it: ASIC design flows on Synopsys Fusion Compiler and Cadence Innovus, SystemVerilog/UVM verification, and SONiC on the software side. Active work on 224G PAM4 SerDes, UCIe die-to-die links and CoWoS chiplet packaging points to a multi-die switch ASIC. Hiring is accelerating and senior-heavy, concentrated in engineering.
Eridu is a privately held networking hardware company founded in 2024 and headquartered in Saratoga, California. It develops network switches for scale-out and scale-up fabrics inside AI clusters and data centers, targeting the communication bottlenecks that limit AI workload performance. The company employs 51–200 people and hires in the United States. Its engineering spans chip design, high-speed I/O, packaging, system hardware and network software.
Eridu uses ASIC and FPGA design tools including Synopsys Fusion Compiler, Cadence Innovus, Verilog, SystemVerilog and UVM, plus SerDes and PCI Express IP, SONiC, C++, Python and Robot Framework.
Eridu is developing 224G PAM4 SerDes, PCIe and UCIe die-to-die support, CoWoS-based multi-die chiplet packaging, and high-speed optical and electrical I/O subsystems for AI networking.
Eridu is headquartered in Saratoga, California, United States, and currently hires in the United States, mainly senior engineering talent.
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Eridu's technology stack, projects, and hiring signals are inferred from public hiring and company data — career pages, public listings, and company web presence — then clustered and de-duplicated. Figures are estimates that refresh over time. Read our full methodology →
This is not an official vendor or customer list. It is a technology-adoption signal inferred from public data, intended for B2B research.
