Arago designs custom silicon and optical accelerators for AI workloads, operating across ASIC, FPGA, and kernel-level integration. The tech stack—SystemVerilog, Cadence tools, RISC-V, PyTorch, CUDA—reflects a hardware-focused engineering org building physical compute, not software. Active hiring across engineering, kernel drivers, and chip verification, with notable gaps in senior technical talent and people operations scaling, suggests a young hardware team racing to tape-out while building foundational ops from scratch.
Notable leadership hires: Head of People
Arago is a semiconductor and photonics platform company designing custom AI accelerators. Based in Paris with operations in Israel, the company targets GPU-scale compute density through optics-enhanced silicon. The engineering roadmap spans full-chip physical design, optical verification, tensor unit integration, and kernel drivers for bare-metal and virtualized access (QEMU/KVM). Early-stage operations reflect a 11–50 person team navigating hardware timelines and multi-geography scaling.
Hardware design: SystemVerilog, Verilog, RISC-V, ASIC, FPGA, Cadence Innovus/Virtuoso. Verification and simulation: UVM, QEMU, KVM. AI/ML: PyTorch, CUDA, LLVM/MLIR. System-level: kernel drivers, MPI, Slurm, LSF.
Next-generation optical chip verification, custom tensor unit integration, full-chip and block-level physical design, kernel drivers for accelerator access, virtualized accelerator isolation (QEMU/KVM), and multiphysics computation unit development.
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Arago's technology stack, projects, and hiring signals are inferred from public hiring and company data — career pages, public listings, and company web presence — then clustered and de-duplicated. Figures are estimates that refresh over time. Read our full methodology →
This is not an official vendor or customer list. It is a technology-adoption signal inferred from public data, intended for B2B research.