Arago is a semiconductor and AI hardware company building custom accelerators at the intersection of photonics and traditional silicon. The tech stack reveals a full-stack hardware design operation: Verilog/SystemVerilog for RTL, Cadence tools for physical design and verification, RISC-V and custom tensor units for compute, and a software layer spanning PyTorch, CUDA, LLVM/MLIR, and distributed systems primitives (MPI, NCCL). Active projects span post-silicon validation, optical chip verification, and multi-node clustering protocols—indicating a move from single-device prototypes toward production-scale systems. Engineering-heavy hiring (19 of 21 roles) skews senior and mid-level, typical of deeptech hardware companies navigating the gap between architecture and manufacturable silicon.
Arago designs custom accelerator hardware and the foundational software stack to run distributed compute across heterogeneous devices. Based in Paris with operations in Israel and the US, the company operates across chip design (mixed-signal IC layout, ASIC development), optical integration, and system-level validation. The engineering organization is focused on prototype-to-product iteration, including debugging tooling, multi-physics simulation, and resource-sharing protocols. The stated pain points—scaling to multi-node clusters, bridging host systems to hardware, and ensuring accessibility across deployment environments—suggest the company is addressing both engineering challenges in production systems and go-to-market friction around hardware provisioning and usability.
Arago uses Verilog/SystemVerilog for design, Cadence Virtuoso and Innovus for layout/verification, RISC-V and custom tensor units for compute, PyTorch/CUDA for ML, and LLVM/MLIR for compilation. System software spans Linux, Slurm, MPI, and NCCL for distributed computing.
Active projects include post-silicon validation and bring-up, optical chip verification, custom tensor unit integration, multi-node accelerator clustering, and foundational software stacks for next-generation HPC hardware. The company is also developing debugging tooling and resource-sharing protocols across heterogeneous devices.
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