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江苏星宇芯联电子科技有限公司 Tech Stack

Chip design and EDA tools integration for semiconductor tapeout

Software Development 南京市, 江苏省 ~5 employees

江苏星宇芯联 is a small hardware design firm operating at the intersection of EDA tooling and semiconductor manufacturing. The tech stack—Virtuoso, Cadence, Xilinx, Altera, Verilog, Design Compiler, VHDL—reflects a tapeout-focused workflow centered on commercial design automation platforms. Active projects span chip feasibility studies, digital circuit verification, and tapeout execution, with internal focus on domestic chip product adoption and compliance.

Tech Stack 12 technologies

Core StackLinux Virtuoso Calibre Xilinx Altera Verilog Cadence VHDL Design Compiler Unix C ZYNQ

What 江苏星宇芯联电子科技有限公司 Is Building

◆Challenges

Ensuring tapeout compliance

▲Active Projects

Exhibition planning and implementation
Chip project feasibility study
System design
Digital circuit design and verification
Tapeout project
Domestic chip product line application
Design import of domestic chip product line
Technical training and product promotion

Hiring Activity

Minimal10 roles · 0 in 30d

Department

Engineering

Sales

Seniority

Mid

Manager

Senior

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About 江苏星宇芯联电子科技有限公司

江苏星宇芯联 provides chip design services and EDA integration for semiconductor development teams in China. The company operates a small, engineering-led organization (9 engineers, 2 sales) concentrated in mid- and senior-level roles, based in Nanjing. Current work centers on semiconductor tapeout projects, domestic chip product line qualification, and digital circuit design verification. The pain-point data signals active navigation of manufacturing compliance workflows.

Headquarters南京市, 江苏省

Company Size~5 employees

Hiring MarketsChina

Frequently Asked Questions

What EDA tools does 江苏星宇芯联 use?

Cadence Virtuoso, Design Compiler, Xilinx Vivado, and Altera tools. Design work spans Verilog and VHDL with Unix/Linux development environments.

What projects is 江苏星宇芯联 working on?

Active work includes chip feasibility studies, digital circuit design and verification, tapeout execution, and domestic chip product line qualification and integration.