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Tessolve Tech Stack
Semiconductor design and validation services for ASIC and embedded systems
Tessolve delivers pre-silicon design and post-silicon validation services for semiconductor and embedded product development. The stack reveals a classical EDA-heavy semiconductor shop: SystemVerilog, UVM, Synopsys, Cadence, and Xcelium dominate the validation layer, paired with C/C++ and Python for tooling and analysis. Active projects cluster around design-for-test (DFT), DDR/interface validation, and SoC verification — the engineering-dominant hiring mix (95% of open roles, heavily senior) reflects a services firm scaling validation capacity on complex silicon.
Tech Stack 113 technologies
Core StackPython Pandas NumPy SystemVerilog UVM C/C++ Perl Xcelium Questa Bash Tcl Synopsys Cadence IC Compiler Innovus Tempus C AXI GPIO I2C UART PCIe USB Synopsys VCS Cadence Incisive TCL Ethernet SerDes NVMe Calibre+80 more
AdoptingUVM
What Tessolve Is Building
◆Challenges
- Reducing expensive re-design costs
- Optimizing multi-die procedures
- Timing closure
- System-level issues
- Audio quality assurance
- Managing complex software projects
- Ensuring timely delivery
- Maintaining high-quality standards
- Reducing time-to-market
- Time-to-market for advanced semiconductor technologies
▲Active Projects
- Post-silicon validation
- Soc/asic projects
- Dft atpg implementation for soc
- Ddr controller validation
- Dft architecture definition and implementation for soc/asic designs
- Develop and integrate scan, mbist, lbist, boundary scan, and atpg solutions
- Own dft strategy from rtl to silicon, including test planning, insertion, simulation, and verification
- Audio validation framework for android devices
- Audio artifact detection automation
- Ip and soc interface verification
Hiring Activity
Steady80 roles · 30 in 30d
Department
Seniority
Notable leadership hires: Lead Engineer, RTL Design Lead, Design Lead, Technical Lead
Company intelligence
