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NextSilicon Tech Stack
Custom silicon and compiler stack for AI and HPC workloads
NextSilicon designs application-specific processors and the software stack to run them. The tech footprint—MLIR, LLVM, PyTorch/TensorFlow compilers, CUDA/ROCm, and EDA tools (Synopsys, Cadence)—shows a company building from silicon up through AI inference and HPC optimization. The hiring profile is heavily senior and lead engineers (27 of 30 in engineering), signaling deep technical work on custom hardware-software integration rather than scaling operations.
Tech Stack 73 technologies
Core StackPython C++ Linux PyTorch TensorFlow Ruby Perl Tcl GDSII C MLIR LLVM CUDA ROCm OpenCL C/C++ Bash OpenMP OpenACC Kokkos MPI LLaMA DeepSeek MLPerf Triton IREE XLA ONNX Synopsys Cadence+43 more
AdoptingMLIR
What NextSilicon Is Building
◆Challenges
- Optimizing hpc workloads for custom hardware
- Meeting challenging area timing layout targets
- Debugging lvs and drc issues
- Bottlenecks in timing closure
- Aggressive back-end initiatives
- Optimizing large-scale ai workloads
- Hardware/software bottlenecks
- Cross-stack performance optimization
- Tight product delivery schedules
- Adapting software to hardware acceleration
▲Active Projects
- Next-generation runtime compiler
- Pioneering architecture for a general-purpose coprocessor
- Leading aggressive back-end initiatives
- System software support for next generation maverick system
- Mlir-based ai compiler stack
- High-performance backend for pytorch and tensorflow
- Automated optimization process for hpc applications
- Ai framework and compiler stack development
- Nextsilicon parallel compute framework api architecture
- Asic chip timing closure
Hiring Activity
Minimal35 roles · 4 in 30d
Department
Seniority
Company intelligence
