Chiplet interconnect IP for modular semiconductor systems
Baya Systems designs on-chip fabric and communication IP to enable interoperability across chiplet-based systems. The stack—Verilog, SystemVerilog, UVM, Synopsys Design Compiler, targeting TSMC and Intel Foundry—reflects a hardware-focused org executing at production scale. Hiring skews heavily toward senior engineers (23 of 26 engineering roles) across four countries, with parallel IPO-readiness and finance scaling projects, signaling transition from startup mode toward institutional maturity.
Baya Systems, founded in 2023 and headquartered in Santa Clara, develops modular semiconductor IP addressing the architectural fragmentation of chiplet-based compute. The core product is on-chip fabric and communication technology that allows industry-standard protocols and components to interoperate without performance loss. The company serves semiconductor and systems designers building multi-chiplet systems. Active projects include configurable IP blocks for caches, memory subsystems, interconnects, and network-on-chip (NoC) architectures, as well as customized solutions for customer-specific implementations. The organization is preparing for IPO while scaling IP licensing and design-in velocity globally.
Baya uses Verilog, SystemVerilog, Python, UVM, AXI, Synopsys Design Compiler, and PCIe. The design targets TSMC and Intel Foundry process nodes.
Baya designs chiplet interconnect IP and on-chip fabric that enables interoperability across semiconductor subsystems. The IP targets configurable microarchitectures, caches, memory, and interconnects for multi-chiplet systems.
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