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Timesintelli Technology Tech Stack
Edge AI chip designer building custom processors for IoT and vision applications
Timesintelli designs fabless edge AI chips and solutions for IoT devices, with engineering talent concentrated in hardware design (Verilog, SystemVerilog, Synopsys EDA stack) and processor architecture (RISC-V, NPU microarchitecture). The project mix—model quantization, NPU definition, USB/eMMC subsystems, chip SDK development—reflects a company moving from core processor design toward full-stack solutions. Hiring velocity is minimal and concentrated in senior engineering roles, suggesting a stable, specialized team focused on depth rather than scaling headcount.
Tech Stack 32 technologies
Core StackLinux Python TensorFlow PyTorch Verilog SystemVerilog USB ARM C/C++ ONNX Caffe OpenCV CDC Innovus Calibre Virtuoso Perl Tcl UVM Makefile RISC-V MIPS C RTOS TCL FreeRTOS UART I2C Synopsys USB 3.0+2 more
What Timesintelli Technology Is Building
◆Challenges
- Meeting sales targets
- Improving customer satisfaction
- Model quantization and compression
- Ai model performance optimization on npu
▲Active Projects
- Model quantization tool development
- Model conversion tool development
- Usb/emmc subsystem design
- New product launch
- Key customer onboarding
- Npu microarchitecture definition
- Vision processor performance analysis
- Rtl coding for processor submodules
- Chip sdk component development
- Chip solution promotion
Hiring Activity
Minimal25 roles · 1 in 30d
Department
Seniority
Company intelligence
