SiFive Tech Stack

RISC-V CPU and SoC design IP for next-generation computing platforms

Semiconductor Manufacturing Santa Clara, California 501–1,000 employees Privately Held

SiFive designs and manufactures RISC-V-based processor IP and full-chip implementations. The stack reveals a deep hardware-verification operation: Verilog, SystemVerilog, UVM, and FPGA tooling dominate, paired with CI/CD automation (Jenkins, pytest, Robot Framework) and simulation (QEMU). The engineering-heavy hiring mix (15 of 19 roles) skews toward staff and senior IC designers, and active projects span RTL-to-GDSII physical implementation—indicating SiFive is scaling from IP licensing into full chip tapeout services. Pain points around RISC-V adoption and AI CPU performance suggest the market is still early, and SiFive is building both the toolchain maturity and performance benchmarks to drive broader ecosystem use.

Tech Stack 32 technologies

Core StackGitHub Jenkins Jira Grafana Python C++ Make Scala Linux Git Robot Framework pytest Bash C CMake Yocto QEMU FPGA SystemVerilog UVM Verilog Makefiles RISC-V Zoom Rooms Jamf GDSII JasperGold VHDL U-Boot Yocto Project+2 more

AdoptingScala RISC-V

What SiFive Is Building

◆Challenges

Adoption of risc-v
Improving automation in ar and gl processes
Debug trace profiling hardware
Fast time-to-market
State of the art debug strategy
Adopting risc-v for soc designs
Achieving high-performance ai cpus
Analyzing cpu microarchitecture bottlenecks
Optimizing workload performance

▲Active Projects

Enhance debug/trace/profiling hardware
Develop new debug/trace/profiling capabilities
Testing toolchain/linux/library/ml software on qemu/fpga
Ci/cd test automation pipelines
Scalable constrained random test bench
In-house verification ip for memory subsystem
Test benches and suites for execution
Risc-v cpu implementation from rtl to gdsii
Physical implementation flow development
Engagement with risc-v international association

Hiring Activity

Decelerating20 roles · 5 in 30d

Department

Engineering

Finance

Support

Seniority

Staff

Senior

Lead

Mid

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About SiFive

SiFive creates RISC-V processor IP cores and complete SoC designs for semiconductor and system companies. The company operates across three layers: foundational IP (CPU cores, memory subsystems, debug/trace hardware), design automation and verification (in-house test infrastructure, CI/CD pipelines), and physical implementation (RTL-to-GDSII flow). Based in Santa Clara with engineering offices in India, the UK, and France, SiFive serves customers building next-generation CPUs, embedded processors, and AI accelerators on the RISC-V instruction set. The organization is primarily engineering-driven, with active focus on reducing time-to-market and improving verification automation across register and gate-level design processes.

HeadquartersSanta Clara, California

Company Size501–1,000 employees

Hiring MarketsIndia, United Kingdom, France, United States

Frequently Asked Questions

What is SiFive's tech stack?

SiFive uses Verilog, SystemVerilog, UVM, FPGA, and QEMU for hardware design and verification; Git, GitHub, Jenkins, Jira, pytest, and Robot Framework for CI/CD and build automation; and GDSII, JasperGold, and custom tooling for physical implementation and formal verification.

What is SiFive working on?

SiFive is developing RISC-V CPU implementations from RTL to GDSII, advancing debug/trace/profiling hardware, building scalable test automation and verification IP for memory subsystems, and optimizing AI CPU performance and workload execution on RISC-V architectures.