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Racyics Tech Stack

System-on-Chip design services for advanced semiconductor nodes

Semiconductor Manufacturing Dresden 51–200 employees Founded 2009 Privately Held

Racyics is a chip design services firm focused on mixed-signal and digital SoC development at leading-edge nodes. The tech stack is anchored in Cadence and Synopsys tools (Virtuoso, Allegro, APD) paired with hardware description languages (Verilog, SystemVerilog, VHDL) and verification frameworks (UVM), reflecting a mature ASIC design operation. The hiring profile—concentrated entirely in engineering with a spread across junior through principal levels—suggests active project delivery rather than scaling headcount.

Tech Stack 20 technologies

Core StackPython Siemens Cadence Allegro Cadence APD Altium Designer CST Studio Suite Ansys HFSS Ansys SIwave Cadence Virtuoso Perl TCL VBA VHDL Verilog SystemVerilog UVM JTAG Cadence Synopsys Ansys

What Racyics Is Building

◆Challenges

Designing socs in leading edge technologies

▲Active Projects

Chip and block level functional verification
Rtl2gds flow optimization
Verification methodology enhancement
Soc design projects
Mixed-signal circuit design
Physical design, implementation and verification of complex digital and mixed signal socs
Methodology development and flow enhancement

Hiring Activity

Minimal9 roles · 0 in 30d

Department

Engineering

9

Seniority

Junior

3

Mid

2

Senior

2

Intern

1

Principal

1

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About Racyics

Racyics delivers custom System-on-Chip design services to German and international semiconductor companies, working on complex analog, digital, and mixed-signal designs at advanced process nodes. The company operates a turnkey design flow covering functional verification, RTL-to-GDS optimization, and physical implementation. Located in Dresden next to the Technical University of Dresden, Racyics maintains partnerships with both foundries and fabless design houses, offering both standalone design services and collaborative engagements. Current project work spans chip and block-level verification, methodology enhancement, and the physical design of complex multi-domain SoCs.

HeadquartersDresden

Company Size51–200 employees

Founded2009

Hiring MarketsGermany

Frequently Asked Questions

What EDA tools does Racyics use?

Cadence Virtuoso, Cadence Allegro, Cadence APD, Synopsys tools, Ansys HFSS, Ansys SIwave, and CST Studio Suite for electromagnetic and signal-integrity simulation across the design flow.

Is Racyics hiring engineers?

Nine active engineering roles open across junior, mid, senior, and principal levels, with minimal hiring velocity in the past 30 days. All positions are based in Germany.

What does Racyics specialize in?

Mixed-signal and digital SoC design services at leading-edge technology nodes, including functional verification, RTL-to-GDS flow optimization, physical design, and custom IP development for foundry-based and fabless customers.