Quadric Tech Stack
AI processor IP for on-device inference with unified scalar-vector-matrix execution
Quadric designs a general-purpose neural processing unit (GPNPU) architecture that runs AI inference and C++ code on a single processor—eliminating the traditional software partitioning burden across multiple chips. The tech stack reveals a compiler-heavy, hardware-focused operation: LLVM, MLIR, SystemVerilog, Verilog, and both Synopsys and Cadence EDA tooling dominate the build. Active adoption of vLLM, ONNX Runtime, and ExecuTorch signals a push toward broader model compatibility. The hiring surge (29 roles posted in 30 days, engineering-dominant) and project backlog—ISO 26262 certification, PPA optimization, quantization workflows—show a company scaling to meet automotive safety and power-efficiency demands.
Tech Stack 50 technologies
What Quadric Is Building
◆Challenges
- Meeting iso 26262 certification
- Ppa optimization across ip configurations
- Optimizing neural networks on quadric epu
- Building scalable reference flows
- Troubleshooting integration issues
- Technical support for complex hardware/software
- Optimizing quantization for custom hardware
- Balancing accuracy, latency, power, memory trade-offs
- Safety-critical compliance of ai compiler stack
- Scalable reference flow development
▲Active Projects
- Ppa optimization
- Lowering and optimizing neural networks on the quadric epu
- Quadric kernel library development
- Iso 26262 certification testing
- Eda tool qualification and benchmarking
- Quadric toolchain, compiler and runtime improvement
- Numerical accuracy testing infrastructure
- Quantization workflows for vision and language models
- Tcl and python automation
- Tool qualification for automotive safety
