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Neurophos Tech Stack

Photonic AI chips delivering exascale inference at GPU power budgets

Computer Hardware Austin, Texas 11–50 employees Founded 2020 Privately Held

Neurophos builds optical processors for AI inference, compressing the compute density of large server racks into a single GPU-sized package. The company is hiring 27 engineers—mostly at lead and principal levels—across a tight stack of silicon photonics, ASIC design, and compiler work (PyTorch, JAX, Triton). Current projects center on GEMM optimization, 4-bit quantization, and porting large language models to optical inference, suggesting a near-term push toward production LLM acceleration.

Tech Stack 30 technologies

Core StackJenkins GitLab CI/CD GitHub Actions Python Linux PyTorch GitHub Hugging Face C++ Cadence Virtuoso ASIC SerDes FPGA Triton JAX SystemC UEFI Secure Boot Open Compute Project Verilator SystemVerilog Silicon Photonics C UVM Xcelium JasperGold Git Cadence Xilinx Vivado PCIe

What Neurophos Is Building

Challenges

  • Power wall
  • Rising energy consumption and costs
  • Power and scalability challenges
  • Outpacing energy capacity
  • Energy capacity constraints
  • High energy consumption in data centers
  • Energy capacity bottleneck
  • Physical limits of silicon
  • Scalability challenges in data centers
  • Energy capacity shortfall

Active Projects

  • Optical gemm engine modeling
  • Developing quantization strategies for 4-bit precision
  • Custom processor core design for opu
  • Optimizing gemm operations
  • Llm accelerator compiler development
  • Porting llms to optical inference engines
  • Trace-driven simulation infrastructure
  • Performance modeling infrastructure
  • Sram vector processor modeling
  • System-on-chip programs

Hiring Activity

Accelerating30 roles · 20 in 30d

Department

Engineering
27
Legal
1
Marketing
1
Product
1

Seniority

Lead
9
Principal
7
Staff
4
Director
3
Senior
3
Mid
2
VP
2

Notable leadership hires: Director of Marketing, Functional Modeling Lead, Tech Lead, Optics Director

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About Neurophos

Neurophos designs the OPU, an optical processor that replaces conventional silicon for AI workloads. The chip trades electrical transistors for photonic ones, routing compute through light rather than electrons, which reduces power consumption and physical footprint dramatically—millions of weights fit in postage-stamp-sized areas where conventional silicon would need a full square meter. Founded in 2020 and based in Austin, the company is backed by a small but specialized engineering organization focused on the hardware, compiler, and modeling layers required to bring photonic AI to market.

HeadquartersAustin, Texas
Company Size11–50 employees
Founded2020
Hiring MarketsUnited States

Frequently Asked Questions

What tech stack does Neurophos use?

Neurophos uses Cadence Virtuoso and SystemVerilog for chip design, PyTorch/JAX/Triton for ML frameworks, Jenkins and GitLab CI/CD for build, and Xcelium for simulation. The stack reflects deep specialization in photonic ASIC design and AI compiler development.

What is Neurophos working on?

Current projects include optical GEMM engine modeling, 4-bit quantization strategies, custom processor core design, LLM compiler development, and porting large language models to optical inference engines. The company is also building trace-driven and performance modeling infrastructure.

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