Low-power FPGA and programmable logic for edge, industrial, and datacenter markets
Lattice Semiconductor designs and manufactures FPGAs and CPLDs for edge, industrial, automotive, and datacenter applications. The tech stack reveals a shift toward infrastructure-as-code (Terraform, Ansible, Docker, Kubernetes) and AI-adjacent tooling (RAG adoption), while active projects span silicon feature work, power optimization, and datacenter control—signaling product expansion beyond traditional edge into cloud infrastructure. Engineering-heavy hiring (105 of 131 roles) concentrated in senior and staff levels points to complexity scaling: yield improvement, test-time reduction, and design-efficiency gaps are flagged as live operational challenges.
Notable leadership hires: Director Planning
Lattice Semiconductor is a publicly traded (NASDAQ: LSCC) fabless semiconductor company headquartered in Hillsboro, Oregon. Founded in 1983, the company specializes in low-power programmable logic devices (FPGAs, CPLDs) sold into communications, computing, industrial, automotive, and consumer segments. Manufacturing and R&D operations span the US, China, Philippines, and Malaysia. The product portfolio addresses power-constrained environments: edge nodes, IoT devices, and increasingly, datacenter infrastructure. Distribution channels combine direct sales and design partnerships; customers include OEMs and systems integrators across embedded and cloud-edge boundaries.
Core: FPGA design (Verilog, SystemVerilog, VHDL), DSP, DDR4/DDR5/LPDDR4 memory controllers, SERDES, PCIe, Ethernet. Tooling: C/C++, Python, Bash, TCL, Jenkins. Adopting: Terraform, Ansible, Docker, Kubernetes, CMake, RAG. Microsoft enterprise suite (365, Defender, Sentinel, Entra ID) for security/compliance.
Current focus: connectivity IP portfolio, power optimization benchmarking, silicon feature work (IO/memory/SERDES), FPGA primitives and IP development, high-speed RTL design, and datacenter control solutions. Also addressing operational challenges: yield improvement, test-time reduction, design efficiency, and post-release customer issues.
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