Semiconductor test instrumentation and ATE solutions for power devices and SoCs
Beijing Huafeng builds automated test equipment (ATE) for semiconductor validation, with particular focus on power semiconductor devices and system-on-chip (SoC) designs. The stack—HFSS, Cadence, Vivado, ModelSim across FPGA and PCIe/DDR4 interfaces—reflects a hardware-focused engineering org optimized for test board design and instrument control. Active challenges around test cost reduction and fault coverage expansion suggest the product roadmap is driven by manufacturing yield economics rather than feature expansion.
Huafeng Huafeng develops automated test equipment and ATE solutions for semiconductor manufacturers and design validation teams in China. The company operates across power semiconductor device testing, SoC test boards (including Accotest integration), and embedded power control firmware. Core offerings span test instrument hardware, PCIe/DDR4-based test interfaces, and ModelSim/Vivado-based validation flows. The engineering-heavy org (33 of 37 headcount) with mid-level seniority emphasis indicates a mature product with incremental optimization cycles rather than greenfield platform development.
Cadence, HFSS, Vivado, ModelSim, MATLAB/Simulink for instrument modeling; FPGA (Xilinx), PCIe, DDR4, and C/VHDL/Verilog for hardware implementation. Backend: Linux, Nginx, MySQL, Redis for test automation and data collection.
Power semiconductor test instruments, SoC ATE solutions (including Accotest design), test board development, power supply design, and embedded control firmware. Current focus areas include reducing test cost and increasing fault coverage in validation workflows.
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