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EnCharge AI Tech Stack
In-memory AI accelerator hardware with custom compiler stack
EnCharge AI designs custom silicon for AI inference, built around in-memory computing architecture paired with a next-generation compiler stack (Torch-MLIR, XLA, LLVM). The hiring profile is heavily weighted toward principal and senior hardware engineers (13 principal roles), reflecting the maturity and depth required for post-silicon validation, timing closure on advanced nodes, and chiplet-based system integration. Active adoption of Llama alongside projects spanning SoC floorplanning, custom NPU kernel libraries, and AI serving infrastructure suggests a shift from pure accelerator design toward end-to-end inference deployment.
Tech Stack 35 technologies
Core StackC++ Python GitHub Actions GitLab CI/CD Jenkins Linux PCIe RISC-V SystemVerilog UVM MPI pthreads Torch-MLIR XLA LLVM GPU MLIR Cadence TCL LPDDR4 LPDDR5 Tcl Synopsys TestMAX bash Red Hat Ubuntu NFS SMB Innovus IC Compiler II+4 more
AdoptingLlama
What EnCharge AI Is Building
◆Challenges
- Balancing aggressive performance targets
- Eliminating systemic bottlenecks
- Graph compilation
- Performance parity across models
- Meeting stringent timing targets
- Ensuring manufacturable chips
- Balancing performance and power
- Minimizing area overhead
- Timing closure on advanced process nodes
- Performance optimization of simulation
▲Active Projects
- High-speed soc implementation
- Chip-level floorplanning for complex socs
- Serving infrastructure for video generation models
- Chiplet-based ai inference platform
- Next-generation ai compiler and software stack
- Kernel library integration for custom npu ops
- Post-silicon validation and bring-up
- Scalable multi-core simulation model
- Timing closure strategy for soc and ip designs
- Simulation infrastructure optimization
Hiring Activity
40 roles · 25 in 30d
Department
Seniority
Notable leadership hires: Physical Design Lead
Company intelligence
