AI inference accelerator hardware and compiler stack for datacenters
d-Matrix designs custom silicon and system software for AI inference workloads at datacenter scale, using a deep hardware-software stack spanning SystemVerilog, RISC-V, CUDA, PyTorch, and MLIR-based compiler tooling. The hiring profile is nearly 100% engineering-heavy with significant staff and principal seniority, concentrated on chip design (SOC verification, tape-out) and compiler infrastructure — typical of a semiconductor startup executing a multi-year hardware development cycle. Active pain points around inference latency, memory efficiency, and secure datacenter integration reveal the core technical challenges blocking their path to production.
d-Matrix builds Corsair, a specialized compute platform for running large language model inference in datacenters at higher throughput and lower power than general-purpose accelerators. The company operates as a full-stack semiconductor firm: designing custom silicon (verified in UVM/SystemVerilog), developing runtime firmware and kernel software for their multiprocessor systems-on-chip, and building compiler infrastructure (MLIR-based) to optimize inference workloads. Founded in 2019 and based in Santa Clara, the company employs 51–200 people and is actively hiring across engineering roles in the United States, India, Canada, and Australia. Their roadmap includes productizing their software stack, scaling compiler tooling, and integrating security features to meet datacenter deployment requirements.
d-Matrix uses SystemVerilog and UVM for chip design, RISC-V and PCIe 5.0 for hardware architecture, C/C++ and Python for software, PyTorch and vLLM for AI frameworks, and MLIR-based compilers for inference optimization. CAD tools include Cadence for design.
d-Matrix is focused on productizing their AI inference compute engine, building compiler infrastructure (MLIR-based), executing SOC design and tape-out, developing runtime firmware for multiprocessor systems, and creating hardware diagnostic tools for their novel accelerator stack.
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