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d-Matrix Tech Stack

AI inference accelerator platform and chip design for datacenter deployments

Semiconductor Manufacturing Santa Clara, California 51–200 employees Founded 2019 Privately Held
d-matrix.ai LinkedIn

d-Matrix designs custom silicon (Corsair) purpose-built for AI inference, with a tech stack spanning PyTorch, TensorFlow, FPGA, RISC-V, SystemVerilog, and Cadence — the full depth required for chip-to-cloud productization. The hiring mix (37 engineers across staff, senior, and principal levels; only 3 ops) and active projects (compiler infrastructure, SoC verification, tape-out, CI/CD) show a company mid-cycle in hardware engineering, now shifting focus to software productization and supply-chain automation as they scale from design into manufacturing.

Tech Stack 109 technologies

Core StackPython PyTorch TensorFlow scikit-learn Pandas NumPy Oracle Matplotlib FPGA C/C++ CUDA MLIR LLVM Tensilica SAP IBP Kinaxis Anaplan SystemVerilog UVM SystemC RISC-V PCIe 5.0 Bash Raspberry Pi Zephyr Ubuntu TCP/IP GPIO UART Cadence+78 more
AdoptingOpenShift

What d-Matrix Is Building

◆Challenges

  • Productizing sw stack
  • Complex software/hardware integration
  • Tight development window
  • Improving manufacturing workflows
  • Inventory reconciliation
  • Bom risk analysis
  • Stranded inventory
  • Reducing manual effort across product generations
  • Optimizing manufacturing test efficiency
  • Identifying yield-limiting patterns

▲Active Projects

  • Productize ai compute engine software stack
  • Compiler infrastructure development
  • Board-level functional test modules for corsair pcie accelerator cards
  • Soc verification environments and tape out efforts
  • Chip development cycle program management
  • In-memory computing architecture
  • Ci/cd pipeline automation
  • Productizing sw stack for ai compute engine
  • Scale operations using ai/automation across supply chain functions
  • Hardware test failure diagnosis ai agent

Hiring Activity

Accelerating45 roles · 20 in 30d

Department

Engineering
37
Ops
3
Operations
2
Construction
1
Logistics
1
Security
1

Seniority

Staff
13
Senior
12
Principal
11
Intern
6
Manager
2
Director
1
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About d-Matrix

d-Matrix builds Corsair, a custom computing platform designed to reduce cost and power consumption for AI inference workloads in datacenters. The company sits at the intersection of semiconductor design and AI software, combining chip architecture work (SoC verification, functional test modules, PCIe accelerator cards) with compiler and software-stack development (MLIR, LLVM-based tooling). Founded in 2019 and based in Santa Clara, the organization spans 51–200 employees across engineering, operations, and logistics, with current hiring momentum concentrated in senior and staff-level engineering roles across the United States, India, Australia, Canada, and Serbia.

HeadquartersSanta Clara, California
Company Size51–200 employees
Founded2019
Hiring MarketsUnited States, India, Australia, Canada, Serbia

Frequently Asked Questions

What technology does d-Matrix use to build AI chips?

d-Matrix uses PyTorch and TensorFlow for ML workloads, SystemVerilog and UVM for chip verification, Cadence for design tools, MLIR and LLVM for compiler infrastructure, and RISC-V and FPGA as foundational architectures.

What is d-Matrix working on?

Current projects include compiler infrastructure development, SoC verification and tape-out efforts for Corsair PCIe accelerator cards, software-stack productization for the AI compute engine, CI/CD automation, and AI-driven supply-chain optimization including manufacturing test efficiency and yield analysis.

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How this profile is built

d-Matrix's technology stack, projects, and hiring signals are inferred from public hiring and company data — career pages, public listings, and company web presence — then clustered and de-duplicated. Figures are estimates that refresh over time. Read our full methodology →

This is not an official vendor or customer list. It is a technology-adoption signal inferred from public data, intended for B2B research.