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Avicena Tech Tech Stack

High-bandwidth optical interconnects for semiconductor systems

Semiconductor Manufacturing Sunnyvale, California 11–50 employees Founded 2019 Privately Held

Avicena Tech designs optical interconnect semiconductors, with a tech stack anchored in Synopsys and Cadence EDA tools—standard for silicon validation and layout. The project list reveals a shift from pure chip design toward system-level concerns: formal verification, advanced packaging, and optomechanical testing alongside core IC development. Pain points (functional correctness, tool uptime, system integration validation) signal they're solving for reliability at higher speeds and lower power, not just tape-out velocity.

Tech Stack 21 technologies

Core StackPython Solidworks SolidWorks Confluence Jira UVM SystemVerilog Perl Synopsys VCS Xcelium Verilog Synopsys Design Compiler Synopsys PrimeTime Cadence Zemax Cadence Virtuoso Calibre FinFET Ansys Microsoft Office Microsoft Project

What Avicena Tech Is Building

◆Challenges

Functional correctness of high-speed low-power ics
Maintaining tool uptime
Customer onboarding challenges
System integration validation challenges
High-speed automated testing

▲Active Projects

Uvm testbench development
Formal verification of cdc
Regression suite management
High-speed, low-power digital ic design for photonics interconnects
Next-generation optical interconnect solutions
Chip tapeout
Optical interconnect development
Connector ecosystem development
Optomechanical test procedure development
Advanced packaging solutions

Hiring Activity

Accelerating10 roles · 5 in 30d

Department

Engineering

10

Manufacturing

1

Seniority

Senior

6

Mid

5

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About Avicena Tech

Avicena Tech develops high-bandwidth semiconductor interconnects for photonic and optical systems. Founded in 2019, the company is based in Sunnyvale, California and operates as a privately held firm with 11–50 employees. The team is engineering-heavy, concentrated in design and verification roles at senior and mid-levels, with active hiring in the United States and United Kingdom. Core work spans digital IC design for photonics, optical interconnect development, connector ecosystems, and advanced packaging—supported by formal verification and regression testing infrastructure.

HeadquartersSunnyvale, California

Company Size11–50 employees

Founded2019

Hiring MarketsUnited States, United Kingdom

Frequently Asked Questions

What EDA tools does Avicena Tech use?

Synopsys (VCS, Design Compiler, PrimeTime) and Cadence (Virtuoso, Xcelium, Calibre) for simulation, synthesis, timing analysis, and physical design. Also uses Zemax and Ansys for optical and mechanical analysis.

What is Avicena Tech working on?

Next-generation optical interconnects, high-speed low-power digital IC design for photonics, formal verification, advanced packaging solutions, and optomechanical test procedures. Also developing connector ecosystems and managing regression suites at scale.