Arteris Tech Stack
Network-on-chip IP and SoC software for semiconductor design automation
Arteris supplies interconnect IP and SoC integration software to chip designers at major technology companies. The tech stack reveals a hardware-focused engineering operation: SystemC, Verilog, SystemVerilog, and Cadence/Synopsys dominate, paired with verification frameworks (UVM) and deployment tools (OpenShift, Jenkins). Active projects span CI/integration, timing analysis, and testbench generation—indicating deep investment in automating the physical design and verification loops that traditionally bottleneck SoC development. The hiring composition is heavily weighted toward engineering (68% of active roles), with senior and staff engineers driving the work, suggesting mature technical complexity and a design-systems mindset.
Tech Stack 52 technologies
What Arteris Is Building
◆Challenges
- Reducing power consumption
- Performance bottlenecks
- Automating assembly and integration of large complex socs
- Migrating legacy documents to confluence
- Accelerating soc development
- Security weaknesses in semiconductor design
- Implement scalable processes
- Optimize close timelines
- Audit compliance
- Interoperability between software and ip
▲Active Projects
- Ci integration
- Physical implementation flow development
- Pipeline insertion algorithm for noc timing analysis
- Deploy interconnect and memory hierarchy solutions
- Define product direction in pct
- High‑parameter noc ip verification
- Register bank compiler
- Adopt emerging accounting standards
- Testbench generation for eda tool
- Produce application notes and white papers
