A
Arteris Tech Stack
Network-on-chip IP and SoC integration software for semiconductor design
Arteris sells interconnect IP and SoC software into the semiconductor design flow, where design complexity and verification effort are the binding constraint. The tech stack (SystemC, Verilog, SystemVerilog, Cadence, Synopsys, UVM) reflects deep EDA tool integration. Hiring is engineering-heavy and accelerating, concentrated in verification, test infrastructure, and GUI tooling — revealing internal focus on scaling their interconnect validation and design-automation surface.
Tech Stack 63 technologies
Core StackC++ Python OpenShift JavaScript Jira Jenkins Confluence NetSuite Siemens Java HubSpot Google Analytics Google Ads SystemC Verilog VHDL SystemVerilog Cadence Synopsys ARM RISC-V UVM Perl AWS X-Ray Qt Mentor Graphics TCL UNIX AXI Tcl+31 more
What Arteris Is Building
◆Challenges
- Improving verification flows
- Improving performance and reliability
- Scalability and performance of gui framework
- Integration with backend systems
- Adoption of best ui/ux practices
- Reducing risk
- Lowering costs
- Improving engineering productivity
- Complex soc integration challenges
- Long design cycles
▲Active Projects
- Highly configurable noc development
- Ongoing test and development infrastructure improvements
- Automated workflows for cross-collaboration engineering teams
- Advanced test bench development for next‑gen interconnect validation
- Rtl verification and coverage planning
- Performance and power‑aware verification
- Complex gui for professional eda application
- Backend integration for eda tools
- Design of advanced hardware components for arteris ip products
- Hardware ip component design
Hiring Activity
20 roles · 20 in 30d
Department
Seniority
Company intelligence
